A digital background calibration technique for interstage gain nonlinearity in pipelined ADCs-Reference-Cited by-同舟云学术

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A digital background calibration technique for interstage gain nonlinearity in pipelined ADCs

Published:2022-02-25 Issue:4 Volume:19 Page:20210571-20210571
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Ding Bowen¹,Miao Peng¹,Li Fei¹,Gu Weiqi¹

Affiliation:

1. Dept. of Information Science and Engineering, Southeast University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/19/4/19_19.20210571/_pdf

Reference30 articles.

1. [1] B. Murmann and B.E. Boser: “A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification,” IEEE J. Solid-State Circuits 38 (2003) 2040 (DOI: 10.1109/JSSC.2003.819167).

2. [2] J.P. Keane, et al.: “Background interstage gain calibration technique for pipelined ADCs,” IEEE Trans. Circuits Syst. I, Reg. Papers 52 (2005) 32 (DOI: 10.1109/TCSI.2004.839534).

3. [3] N. Sun: “Exploiting process variation and noise in comparators to calibrate interstage gain nonlinearity in pipelined ADCs,” IEEE Trans. Circuits Syst. I, Reg. Papers 59 (2012) 685 (DOI: 10.1109/TCSI.2011.2169854).

4. [4] B.D. Sahoo and B. Razavi: “A 12-bit 200-MHz CMOS ADC,” IEEE J. Solid-State Circuits 44 (2009) 2366 (DOI: 10.1109/JSSC.2009.2024809).

5. [5] B.D. Sahoo and B. Razavi: “A 10-b 1-GHz 33-mW CMOS ADC,” IEEE J. Solid-State Circuits 48 (2013) 1442 (DOI: 10.1109/JSSC.2013.2252518).

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Maximum-Likelihood-Estimation-Based Digital Background Calibration Technique for Interstage Gain Error in Pipelined ADCs;2024 9th International Conference on Computer and Communication Systems (ICCCS);2024-04-19

2. A 1.25-GS/s 14-bit pipelined ADC using a current-feedback flipped input buffer and large dither technique to achieve high linearity;IEICE Electronics Express;2024

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