A novel X-filling method for capture power reduction-Reference-Cited by-同舟云学术

A novel X-filling method for capture power reduction

Published:2017 Issue:23 Volume:14 Page:20171093-20171093
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Kim Heetae¹,Oh Hyunggoy¹,Lim Jaeil¹,Kang Sungho¹

Affiliation:

1. School of Electrical and Electronic Engineering, Yonsei University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/14/23/14_14.20171093/_pdf

Reference10 articles.

1. [1] T. Lee and J.-S. Yang: “Physical-aware gating element insertion for thermal-safe scan shift operation,” IEICE Electron. Express 14 (2017) 20161181 (DOI: 10.1587/elex.14.20161181).

2. [2] M. M. Naeini and C. Y. Ooi: “A novel scan architecture for low power scan-based testing,” VLSI Des. 2015 (2015) 264071 (DOI: 10.1155/2015/264071).

3. [3] D. Denget al.: “A novel power-efficient IC test scheme,” IEICE Electron. Express 14 (2017) 20170462 (DOI: 10.1587/elex.14.20170462).

4. [4] S. Almukhaizim and O. Sinanoglu: “Dynamic scan chain partitioning for reducing peak shift power during test,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. 28 (2009) 298 (DOI: 10.1109/TCAD.2008.2009159).

5. [5] S. Kiamehr, et al.: “A layout-aware x-filling approach for dynamic power supply noise reduction in at-speed scan testing,” Proc. IEEE Eur. Test Symp. (2013) (DOI: 10.1109/ETS.2013.6569356).

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