A novel power-efficient IC test scheme-Reference-Cited by-同舟云学术

A novel power-efficient IC test scheme

Published:2017 Issue:13 Volume:14 Page:20170462-20170462
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Deng Ding¹,Chen Xiaowen¹,Guo Yang¹

Affiliation:

1. College of Computer, National University of Defense Technology

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/14/13/14_14.20170462/_pdf

Reference13 articles.

1. [1] N. Parimi and X. Sun: “Design of a low-power D flip-flop for test-per-scan circuits,” CCECE (2004) 777 (DOI: 10.1109/CCECE.2004.1345229).

2. [2] S. Gerstendorfer and H.-J. Wunderlich: “Minimized power consumption for scan-based BIST,” IEEE ITC (1999) 77 (DOI: 10.1109/TEST.1999.805616).

3. [3] X. Zhang and K. Roy: “Power reduction in test-per-scan BIST,” On-Line Testing Workshop (2000) 133 (DOI: 10.1109/OLT.2000.856625).

4. [4] A. Chandra, et al.: “Low power Illinois scan architecture for simultaneous power and test data volume reduction,” DATE (2008) 462 (DOI: 10.1109/DATE.2008.4484724).

5. [5] S. M. Saeed and O. Sinanoglu: “Expedited response compaction for scan power reduction,” IEEE VTS (2011) 40 (DOI: 10.1109/VTS.2011.5783752).

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