SGERC: a self-gated timing error resilient cluster of sequential cells for wide-voltage processor
Author:
Affiliation:
1. Institute of VLSI Design, Zhejiang University
2. State Key Laboratory of ASIC and System, Fudan University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/elex/14/8/14_14.20170218/_pdf
Reference12 articles.
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3. [3] K. A. Bowmanet al.: “Energy-efficient and metastability-immune resilient circuits for dynamic variation tolerance,” IEEE J. Solid-State Circuits 44 (2009) 49 (DOI: 10.1109/JSSC.2008.2007148).
4. [4] S. Valadimaset al.: “Effective timing error tolerance in flip-flop based core designs,” J. Electron. Test. 29 (2013) 795 (DOI: 10.1007/s10836-013-5419-3).
5. [5] Y. Zhang, et al.: “8.8 iRazor: 3-transistor current-based error detection and correction in an ARM Cortex-R4 processor,” IEEE International Solid-State Circuits Conference (ISSCC) (2016) (DOI: 10.1109/ISSCC.2016.7417956).
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