A design method of CPR for wide voltage design
Author:
Affiliation:
1. Smart Sensing R&D Center, Institute of Microelectronics of Chinese Academy of Sciences
2. University of Chinese Academy of Sciences
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/elex/16/15/16_16.20190366/_pdf
Reference30 articles.
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2. [2] T. Zhu, et al.: “SGERC: A self-gated timing error resilient cluster of sequential cells for wide-voltage processor,” IEICE Electron. Express 14 (2017) 20170218 (DOI: 10.1587/elex.14.20170218).
3. [3] S. Borkar and A. A. Chien: “The future of microprocessors,” Commun. ACM 54 (2011) 67 (DOI: 10.1145/1941487.1941507).
4. [4] S. Kim and M. Seok: “Variation-tolerant, ultra-low-voltage microprocessor with a low-overhead, within-a-cycle in-situ timing-error detection and correction technique,” IEEE J. Solid-State Circuits 50 (2015) 1478 (DOI: 10.1109/JSSC.2015.2418713).
5. [5] D. Ernst, et al.: “Razor: A low-power pipeline based on circuit-level timing speculation,” Proc. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36 (2003) 12 (DOI: 10.1109/MICRO.2003.1253179).
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