A 2.4-GHz all-digital phase-locked loop with a pipeline-ΔΣ time-to-digital converter
Author:
Affiliation:
1. College of Electronic Science and Engineering, Nanjing University of Posts and Telecommunications
2. Jiangsu Lixing General Steel Ball Co., Ltd
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/elex/14/6/14_14.20170095/_pdf
Reference10 articles.
1. [1] V. Kratyuket al.: “A digital PLL with a stochastic time-to-digital converter,” IEEE Trans. Circuits Syst. I, Reg. Papers 56 (2009) 1612 (DOI: 10.1109/TCSI.2008.2010109).
2. [2] C. M. Hsuet al.: “A low-noise wide-BW 3.6-GHz digital ΔΣ fractional-N frequency synthesizer with a noise-shaping time-to-digital converter and quantization noise cancellation,” IEEE J. Solid-State Circuits 43 (2008) 2776 (DOI: 10.1109/JSSC.2008.2005704).
3. [3] M. Z. Straayer and M. H. Perrott: “A multi-path gated ring oscillator TDC with first-order noise shaping,” IEEE J. Solid-State Circuits 44 (2009) 1089 (DOI: 10.1109/JSSC.2009.2014709).
4. [4] M. Songet al.: “A 2.4 GHz 0.1-Fref-bandwidth all-digital phase-locked loop with delay-cell-less TDC,” IEEE Trans. Circuits Syst. I, Reg. Papers 60 (2013) 3145 (DOI: 10.1109/TCSI.2013.2265975).
5. [5] R. B. Staszewskiet al.: “Spur-free multirate all-digital PLL for mobile phones in 65 nm CMOS,” IEEE J. Solid-State Circuits 46 (2011) 2904 (DOI: 10.1109/JSSC.2011.2162769).
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