Biasing CMOS amplifiers using MOS transistors in subthreshold region-Reference-Cited by-同舟云学术

Biasing CMOS amplifiers using MOS transistors in subthreshold region

Published:2004 Issue:12 Volume:1 Page:339-345
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Bikumandla Manoj¹,Ramírez-Angulo Jaime¹,Urquidi Carlos¹,Carvajal Ramon G.²,Lopez-Martin Antonio J.³

Affiliation:

1. Klipsch School of Electrical and Computer Engineering, New Mexico State University

2. Grupo de Tecnologia Electrónica, Escuela Superior de Ingenieros, Universidad de Sevilla

3. Departamento de Ingenieria Electrica y Electronica, Universidad Publica de Navarra

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

http://www.jstage.jst.go.jp/article/elex/1/12/1_12_339/_pdf

Reference9 articles.

1. [1] B. Razavi, “Design of Analog CMOS Integrated Circuits, ” McGraw Hill, Boston 2001, Chapter 12.

2. Very Low-Voltage Analog Signal Processing Based on Quasi-Floating Gate Transistors

3. Micropower switched capacitor biquadratic cell

4. UV-activated conductances allow for multiple time scale learning

5. [5] M. Hovin, D. Wisland, Y. Berg, and T. S. Lande, “A Low-Voltage Sinc2 Decimator Implemented by A New Circuit Technique Using Floating-Gate Transistors, ” Proc. of the 2002 IEEE International Symposium on Circuits and Systems, Phoenix, AZ, USA, Paper ID: 0-7803-7448-7/02, pp. V-397-V-400, May 2002.

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