Energy-Aware Multiple-Valued Current-Mode Sequential Circuits Using a Completion-Detection Scheme

Author:

SHIRAHAMA Hirokatsu1,MATSUURA Takashi1,NATSUI Masanori1,HANYU Takahiro1

Affiliation:

1. Research Institute of Electrical Communication, Tohoku University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software

Reference12 articles.

1. [1] “From a few cores to many: A tera-scale computing research overview,” white paper, Intel, 2006; ftp://download.intel.com/research/platform/terascale/terascale_overview_paper.pdf

2. [2] K. Asanovic, et al., “The landscape of parallel computing research: A view from Berkeley,” Technical Report, UCB/EECS-2006-183, Dept. Electrical Eng. and Computer Science, Univ. of Calif., Berkeley, 2006.

3. [3] D. Khalil and Y. Ismail, “A global interconnect link design for many-core microprocessors,” Proc. 1st International Forum on Next-generation Multicore/Manycore Technologies, no.14, 2008.

4. [4] A. Mochizuki, T. Hanyu, and M. Kameyama, “Design of a low-power multiple-valued integrated circuit based on dynamic source-coupled logic,” J. Multiple-Valued Logic and Soft Computing, vol.11, no.5-6, pp.481-498, 2005.

5. [5] A. Mochizuki, H. Shirahama, and T. Hanyu, “Design of a low-power quaternary flip-flop based on dynamic differential logic,” IEICE Trans. Electron., vol.E89-C, no.11, pp.1591-1597, Nov. 2006.

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Highly Reliable Non-volatile Logic Circuit Technology and Its Application;IEICE Transactions on Information and Systems;2014

2. Design and Evaluation of a Differential Switching Gate for Low-Voltage Applications;2013 IEEE 43rd International Symposium on Multiple-Valued Logic;2013-05

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