Highly Reliable Non-volatile Logic Circuit Technology and Its Application-Reference-Cited by-同舟云学术

Highly Reliable Non-volatile Logic Circuit Technology and Its Application

Published:2014 Issue:9 Volume:E97.D Page:2226-2233
ISSN:0916-8532
Container-title:IEICE Transactions on Information and Systems
language:en
Short-container-title:IEICE Trans. Inf. & Syst.

Author:

KIMURA Hiromitsu¹,ZHONG Zhiyong¹,MIZUOCHI Yuta¹,KINOUCHI Norihiro¹,ICHIDA Yoshinobu¹,FUJIMORI Yoshikazu¹

Affiliation:

1. ROHM Co., Ltd.

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software

Link

https://www.jstage.jst.go.jp/article/transinf/E97.D/9/E97.D_2013LOP0017/_pdf

Reference15 articles.

1. [1] L.T. Clark, “Low standby power state storage for sub-130-nm technologies,” IEEE J. Solid-State Circuits, vol.40, no.2, pp.498-506, Feb. 2005.

2. [2] T.-C. Chen, “Where CMOS is going: Trendy hype vs. real technology,” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2006, pp.22-28, 2006.

3. [3] Y. Shin, S. Heo, H.-O. Kim, and J.Y. Choi, “Supply switching with ground collapse: Simultaneous control of subthreshold and gate leakage current in nanometer-scale CMOS circuits,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.15, no.7, pp.758-766, July 2007.

4. [4] Y. Fujimori, T. Nakamura, H. Takasu, H. Kimura, T. Hanyu, and M. Kameyama, “Ferroelectric non-volatile logic devices,” Integrated Ferroelectrics, vol.56, pp.1003-1012, 2003.

5. [5] S. Sugibayashi, R. Nebashi, and N. Kasai, “Nonvolatile magnetic flip-flop for standby-power-free SoCs,” IEEE Custom Integrated Circuits Conf., 2008, pp.14-4-1-14-4-4, 2008.