A Self-Timed SRAM Design for Average-Case Performance-Reference-Cited by-同舟云学术

A Self-Timed SRAM Design for Average-Case Performance

Published:2011 Issue:8 Volume:E94-D Page:1547-1556
ISSN:0916-8532
Container-title:IEICE Transactions on Information and Systems
language:en
Short-container-title:IEICE Trans. Inf. & Syst.

Author:

LEE Je-Hoon¹,SONG Young-Jun²,KIM Sang-Choon¹

Affiliation:

1. Division of Electronics and Information Communication Engineering, Kangwon National University

2. Chungbuk BIT Research-Oriented University Consortium, Chungbuk National University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software

Link

http://www.jstage.jst.go.jp/article/transinf/E94.D/8/E94.D_8_1547/_pdf

Reference13 articles.

1. [1] J. Sparso and S. Furber, Principles of Asynchronous Circuit Design: A Systems Perspective, Kluwer Academic Publishers, 2001.

2. [2] J.H. Lee, Y.H. Kim, and K.R. Cho, “Design of a fast asynchronous embedded CISC microprocessor, A8051,” IEICE Trans. Electron., vol.E87-C, no.4, pp.527-534, April 2004.

3. [3] A.J. Martin, A. Lines, R. Manohar, M. Nystrom, P. Penzes, R. Southworth, U. Cummings, and T.K. Lee, “The design of an asynchronous MIPS R3000 microprocessor,” Proc. 7th Conf. Advance Research in VLSI, pp.164-181, Sept. 1997.

4. [4] J.D. Garside, W.J. Bainbridge, A. Bardsley, D.M. Clark, D.A. Edwards, S.B. Furber, J. Liu, D.W. Lloyd, S. Mohammadi, J.S. Pepper, O. Petlin, S. Temple, and J.V. Woods, “AMULET3i — An asynchronous system-on-chip,” Proc. ASYNC 2000, pp.162-175, April 2000.

5. [5] M.C. Chang and D.S. Shiau, “Design of an asynchronous pipelined processor,” Proc. ICCCAS 2008, pp.1093-1096, May 2008.

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