A Virus Scanning Engine Using an MPU and an IGU Based on Row-Shift Decomposition

Author:

NAKAHARA Hiroki1,SASAO Tsutomu2,MATSUURA Munehiro2

Affiliation:

1. Faculty of Engineering, Kagoshima University

2. Department of Computer Science and Electronics, Kyushu Institute of Technology

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software

Reference25 articles.

1. [1] H.C. Roan, W.J. Hawang, and C.T. Dan Lo, “Shift-or circuit for efficient network intrusion detection pattern matching,” FPL2006, pp.785-790, 2006.

2. [2] J. Ditmar, K. Torkelsson, and A. Jantsch, “A dynamically reconfigurable FPGA-based content addressable memory for internet protocol,” FPL2000, pp.19-28, 2000.

3. [3] P.B. James-Roxby and D.J. Downs, “An efficient content-addressable memory implementation using dynamic routing,” FCCM2001, pp.81-90, 2001.

4. [4] Kaspersky, http://www.kaspersky.com/

5. [5] W. Jiang, Q. Wang, and V.K. Prasanna, “Beyond TCAMs: An SRAM-based parallel multi-pipeline architecture for terabit IP lookup,” INFOCOM2008, pp.1786-1794, 2008.

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