GPU-Accelerated Estimation and Targeted Reduction of Peak IR-Drop during Scan Chain Shifting

Author:

SHI Shiling1,HOLST Stefan1,WEN Xiaoqing1

Affiliation:

1. Kyushu Institute of Technology

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software

Reference27 articles.

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2. [3] X. Lin, “Low power testing-what can commercial design-for-test tools provide?,” J. Low Power Electron. Applicat., vol.1, no.3, pp.357-372, Dec. 2011. 10.3390/jlpea1030357

3. [4] L.-T. Wang, C.-W. Wu, and X. Wen, VLSI Test Principles and Architectures: Design for Testability, Morgan Kaufmann, San Francisco, CA, USA, 2006.

4. [5] X. Wen, Y. Yamashita, S. Kajihara, L.-T. Wang, K.K. Saluja, and K. Kinoshita, “On low-capture-power test generation for scan testing,” Proc. IEEE VLSI Test Symp., pp.265-270, May 2005. 10.1109/vts.2005.60

5. [6] P.K.D. Jagannadha, M. Yilmaz, M. Sonawane, S. Chadalavada, S. Sarangi, B. Bhaskaran, and A. Abdollahian, “Advanced test methodology for complex SoCs,” Proc. IEEE Int. Test Conf., Paper 13.2, Nov. 2016. 10.1109/test.2016.7805857

Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Mitigating Test-Induced Yield-Loss by IR-Drop-Aware X-Filling;2023 IEEE 16th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC);2023-12-18

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