A Data Prefetch and Reuse Strategy for Coarse-Grained Reconfigurable Architectures-Reference-Cited by-同舟云学术

A Data Prefetch and Reuse Strategy for Coarse-Grained Reconfigurable Architectures

Published:2013 Issue:3 Volume:E96.D Page:616-623
ISSN:0916-8532
Container-title:IEICE Transactions on Information and Systems
language:en
Short-container-title:IEICE Trans. Inf. & Syst.

Author:

GE Wei¹,QI Zhi¹,DU Yue¹,MA Lu¹,SHI Longxing¹

Affiliation:

1. National ASIC System Engineering Research Center, Southeast University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software

Link

https://www.jstage.jst.go.jp/article/transinf/E96.D/3/E96.D_616/_pdf

Reference22 articles.

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2. [2] K. Choi, “Coarse-grained reconfigurable array: Architecture and application mapping,” IPSJ Trans. System LSI Design Methodology, vol.4, pp.31-46, 2011.

3. [3] W. Wenjie, L. Leibo, Y. Shouyi, Z. Min, W. Yansheng, and W. Shaojun, “H.264 parallel decoder at hd resolution on a coarse-grained reconfigurable multi-media system,” 10th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), pp.2034-2036, 2010.

4. [4] M. Hartmann, V. Pantazis, T. Vander Aa, M. Berekovic, and C. Hochberger, “Still image processing on coarse-grained reconfigurable array architectures,” J. Signal Processing Systems for Signal Image and Video Technology, vol.60, no.2, pp.225-237, 2010.

5. [5] C. Liang and X.M. Huang, “Mapping parallel fft algorithm onto smartcell coarse-grained reconfigurable architecture,” 20th IEEE International Conference on Application-Specific Systems, Architectures and Processors, pp.231-234, 2009.