Understanding Variations for Better Adjusting Parallel Supplemental Redundant Executions to Tolerate Timing Faults-Reference-Cited by-同舟云学术

Understanding Variations for Better Adjusting Parallel Supplemental Redundant Executions to Tolerate Timing Faults

Published:2014 Issue:12 Volume:E97.D Page:3083-3091
ISSN:0916-8532
Container-title:IEICE Transactions on Information and Systems
language:en
Short-container-title:IEICE Trans. Inf. & Syst.

Author:

SASAGAWA Yukihiro¹,YAO Jun¹,NAKASHIMA Yasuhiko¹

Affiliation:

1. Graduate School of Information Science, Nara Institute of Science and Technology

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software

Link

https://www.jstage.jst.go.jp/article/transinf/E97.D/12/E97.D_2014PAP0024/_pdf

Reference13 articles.

1. [1] T. Kehl, “Hardware self-tuning and circuit performance monitoring,” 1993 Int'l Conference on Computer Design (ICCD-93), pp.188-192, Oct. 1993.

2. [2] A. Uht, “Uniprocessor performance enhancement through adaptive clock frequency control,” 2003 International Conference on Advances in Infrastructure for e-Business, e-Education, e-Science, e-Medicine, and Mobile Technologies on the Internet (SSGRR 2003w), pp.1-10, Jan. 2003.

3. [3] G. Wolrich, E. McLellan, L. Harada, J. Montanaro, and R. Yodlowski, “A high performance floating point coprocessor,” IEEE J. Solid-State Circuits, vol.19, no.5, pp.690-696, Oct. 1984.

4. [4] C.R. Lefurgy, A.J. Drake, M.S. Floyd, M.S. Allen-Ware, B. Brock, J.A. Tierno, and J.B. Carter, “Active management of timing guardband to save energy in POWER7,” Proc. 44th International Symposium on Microarchitecture (MICRO44), pp.1-11, Dec. 2011.

5. [5] T. Burd, T. Pering, A. Stratakos, and R. Brodersen, “A dynamic voltage scaled microprocessor system,” International Solid-State Circuits Conference, pp.1571-1580, Feb. 2000.