1. [1] T. Noll, T. Sydow, B. Neumann, J. Schleifer, T. Coenen, and G. Kappen, “Reconfigurable components for application-specific processor architectures,” in Dynamically Reconfigurable Systems, pp.25-49, Springer Netherlands, 2010.
2. [2] F. Bouwens, M. Berekovic, B.D. Sutter, and G. Gaydadjiev, “Architecture enhancements for the ADRES coarse-grained reconfigurable array,” HiPEAC'08, pp.66-81, Jan. 2008.
3. [3] B. Mei, S. Vernalde, D. Verkest, and R. Lauwereins, “Design methodology for a tightly coupled VLIW/reconfigurable matrix architecture: A case study,” DATE, pp.1224-1229, 2004.
4. [4] D. Burger, S. Keckler, K. McKinley, M. Dahlin, L. John, C. Lin, C. Moore, J. Burrill, R. McDonald, and W. Yoder, “Scaling to the end of silicon with EDGE architectures,” Computer, vol.37, no.7, pp.44-55, 2004.
5. [5] T. Nakada, K. Yoshimura, S. Shitaoka, S. Ooue, D.V. Naveen, and Y. Nakashima, “A linear array accelerator for image processing,” IPSJ Trans. Advanced Computing Systems, vol.5, no.3, pp.74-85, May 2012 (in Japanese).