Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array-Reference-Cited by-同舟云学术

Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array

Published:2008 Issue: Volume: Page:66-81
ISSN:0302-9743
Container-title:High Performance Embedded Architectures and Compilers
language:
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Author:

Bouwens Frank,Berekovic Mladen,De Sutter Bjorn,Gaydadjiev Georgi

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/978-3-540-77560-7_6

Reference12 articles.

1. Mei, B., Vernalde, S., Verkest, D., Man, H.D., Lauwereins, R.: ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix. In: IMEC 2003, Kapeldreef 75, B-3001, Leuven, Belgium (DATE 2004)

2. KressArray, http://kressarray.de

3. SiliconHive, http://www.silicon-hive.com

4. PACT XPP Technologies, http://www.pactxpp.com

5. Singh, H., Lee, M.-H., Lu, G., Kurdahi, F.J., Bagherzadeh, N.: MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications. In: University of California (US) and Federal University of Rio de Janeiro (Brazil), pp. 465–481. IEEE Transactions on Computers, Los Alamitos (2000)

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