Improving the Performance of Circuit-Switched Interconnection Network for a Multi-FPGA System-Reference-Cited by-同舟云学术

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Improving the Performance of Circuit-Switched Interconnection Network for a Multi-FPGA System

Published:2021-12-01 Issue:12 Volume:E104.D Page:2029-2039
ISSN:0916-8532
Container-title:IEICE Transactions on Information and Systems
language:en
Short-container-title:IEICE Trans. Inf. & Syst.

Author:

ITO Kohei¹,IIZUKA Kensuke¹,HIRONAKA Kazuei¹,HU Yao²,KOIBUCHI Michihiro²,AMANO Hideharu¹

Affiliation:

1. Keio University

2. National Institute of Informatics

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software

Link

https://www.jstage.jst.go.jp/article/transinf/E104.D/12/E104.D_2021PAP0002/_pdf

Reference25 articles.

1. [1] K. Hironaka, B.A. Akram, and H. Amano, “Multi-FPGA Management on Flow-in-Cloud Prototype System,” 2019 20th IEEE/ACIS International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing (SNPD), pp.443-448, 2019. 10.1109/snpd.2019.8935738

2. [2] T. Ueno, T. Miyajima, A. Mondigo, and K. Sano, “Hybrid Network Utilization for Efficient Communication in a Tightly Coupled FPGA Cluster,” 2019 International Conference on Field-Programmable Technology (ICFPT), pp.363-366, 2019. 10.1109/icfpt47387.2019.00068

3. [3] N. Fujita, R. Kobayashi, Y. Yamaguchi, and T. Boku, “Parallel Processing on FPGA Combining Computation and Communication in OpenCL Programming,” 2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), pp.479-488, 2019. 10.1109/ipdpsw.2019.00089

4. [4] N. Fujita, R. Kobayashi, Y. Yamaguchi, T. Ueno, K. Sano, and T. Boku, “Performance Evaluation of Pipelined Communication Combined with Computation in OpenCL Programming on FPGA,” 2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), pp.450-459, 2020. 10.1109/ipdpsw50202.2020.00083

5. [5] Y. Hu and M. Koibuchi, “Optimizing Slot Utilization and Network Topology for Communication Pattern on Circuit-Switched Parallel Computing Systems,” IEICE Transactions on Information and Systems, vol.E102-D, no.2, pp.247-260, 2019. 10.1587/transinf.2018edp7225

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