Power Optimized Design Framework for FPGA Clusters-Reference-Cited by-同舟云学术

Power Optimized Design Framework for FPGA Clusters

Published:2024 Issue:0 Volume:17 Page:77-86
ISSN:1882-6687
Container-title:IPSJ Transactions on System and LSI Design Methodology
language:en
Short-container-title:IPSJ Transactions on System LSI Design Methodology

Author:

Iizuka Kensuke¹,Ito Kohei¹,Yasudo Ryota²,Amano Hideharu¹

Affiliation:

1. Keio University

2. Kyoto University

Publisher

Information Processing Society of Japan

Link

https://www.jstage.jst.go.jp/article/ipsjtsldm/17/0/17_77/_pdf

Reference21 articles.

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2. [2] Hironaka, K., Iizuka, K., Yamakura, M., Ahmed, A.B. and Amano, H.: Remote Dynamic Reconfiguration of a Multi-FPGA System FiC (Flow-in-Cloud), IEICE Trans. Information and Systems, Vol.E104-D, No.8, pp.1321-1331 (online), DOI: 10.1587/transinf.2020EDP7165 (2021).

3. [3] Inage, T., Hironaka, K., Iizuka, K., Ito, K., Fukushima, Y., Namiki, M. and Amano, H.: M-KUBOS/PYNQ Cluster for multi-access edge computing, 2021 9th International Symposium on Computing and Networking (CANDAR), pp.1-8 (2021).

4. [4] Goossens, K., Radulescu, A. and Hansson, A.: A Unified Approach to Constrained Mapping and Routing on Network-on-Chip Architectures, 2005 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05), pp.75-80 (online), DOI: 10.1145/1084834.1084857 (2005).

5. [5] Brandner, F. and Schoeberl, M.: Static Routing in Symmetric Real-Time Network-on-Chips, Proc. 20th International Conference on Real-Time and Network Systems, pp.61-70 (2012).