A Generalized Theory Based on the Turn Model for Deadlock-Free Irregular Networks-Reference-Cited by-同舟云学术

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A Generalized Theory Based on the Turn Model for Deadlock-Free Irregular Networks

Published:2020-01-01 Issue:1 Volume:E103.D Page:101-110
ISSN:0916-8532
Container-title:IEICE Transactions on Information and Systems
language:en
Short-container-title:IEICE Trans. Inf. & Syst.

Author:

KAWANO Ryuta¹,YASUDO Ryota¹,MATSUTANI Hiroki¹,KOIBUCHI Michihiro²,AMANO Hideharu¹

Affiliation:

1. Dept. of ICS, Keio University

2. National Institute of Informatics

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software

Link

https://www.jstage.jst.go.jp/article/transinf/E103.D/1/E103.D_2018EDP7367/_pdf

Reference26 articles.

1. [1] J. Kim, W.J. Dally, and D. Abts, “Flattened Butterfly: a Cost-Efficient Topology for High-Radix Networks,” Proc. International Symposium on Computer Architecture (ISCA), pp.126-137, June 2007. 10.1145/1250662.1250679

2. [2] W. Bao, B. Fu, M. Chen, and L. Zhang, “A High-Performance and Cost-Efficient Interconnection Network for High-Density Servers,” Proc. IEEE International Conference on High Performance Computing and Communications & IEEE International Conference on Embedded and Ubiquitous Computing (HPCC_EUC), pp.1246-1253, Nov. 2013. 10.1109/hpcc.and.euc.2013.177

3. [3] M. Besta and T. Hoefler, “Slim Fly: A Cost Effective Low-Diameter Network Topology,” Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), pp.348-359, Nov. 2014. 10.1109/sc.2014.34

4. [4] J.-Y. Shin, B. Wong, and E.G. Sirer, “Small-World Datacenters,” Proc. Symposium on Cloud Computing (SoCC), pp.2:1-2:13, Oct. 2011. 10.1145/2038916.2038918

5. [5] M. Koibuchi, H. Matsutani, H. Amano, D.F. Hsu, and H. Casanova, “A Case for Random Shortcut Topologies for HPC Interconnects,” Proc. International Symposium on Computer Architecture (ISCA), pp.177-188, June 2012. 10.1109/isca.2012.6237016

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