A Threshold Neuron Pruning for a Binarized Deep Neural Network on an FPGA-Reference-Cited by-同舟云学术

A Threshold Neuron Pruning for a Binarized Deep Neural Network on an FPGA

Published:2018 Issue:2 Volume:E101.D Page:376-386
ISSN:0916-8532
Container-title:IEICE Transactions on Information and Systems
language:en
Short-container-title:IEICE Trans. Inf. & Syst.

Author:

FUJII Tomoya¹,SATO Shimpei¹,NAKAHARA Hiroki¹

Affiliation:

1. Department of Information and Communications Engineering, Tokyo Institute of Technology

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software

Link

https://www.jstage.jst.go.jp/article/transinf/E101.D/2/E101.D_2017RCP0013/_pdf

Reference35 articles.

1. [1] S. Anwar, K. Hwang, and W. Sung, “Structured pruning of deep convolutional neural networks,” Computer Research Repository (CoRR), Dec., 2015. https://arxiv.org/ftp/arxiv/papers/1512/1512.08571.pdf

2. [2] Caffe: Deep learning framework, http://caffe.berkeleyvision.org/

3. [3] Chainer: A powerful, flexible, and intuitive framework of neural networks, http://chainer.org/

4. [4] S. Chakradhar, M. Sankaradas, V. Jakkula, and S. Cadambi, “A dynamically configurable coprocessor for convolutional neural networks,” Annual Int'l Symp. on Computer Architecture (ISCA), pp.247-257, 2010. 10.1145/1815961.1815993

5. [5] The CIFAR-10 data set, http://www.cs.toronto.edu/~kriz/cifar.html

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