Fault-Tolerant FPGA: Architectures and Design for Programmable Logic Intellectual Property Core in SoC-Reference-Cited by-同舟云学术

Fault-Tolerant FPGA: Architectures and Design for Programmable Logic Intellectual Property Core in SoC

Published:2015 Issue:2 Volume:E98.D Page:252-261
ISSN:0916-8532
Container-title:IEICE Transactions on Information and Systems
language:en
Short-container-title:IEICE Trans. Inf. & Syst.

Author:

AMAGASAKI Motoki¹,ZHAO Qian¹,IIDA Masahiro¹,KUGA Morihiro¹,SUEYOSHI Toshinori¹

Affiliation:

1. Graduate School of Science and Technology, Kumamoto University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software

Link

https://www.jstage.jst.go.jp/article/transinf/E98.D/2/E98.D_2014RCP0009/_pdf

Reference23 articles.

1. [1] Xilinx Inc., Zynq-7000 All Programmable SoC Overview, June 2012.

2. [2] S.J.E. Wilton, C.H. Ho, B. Quinton, P.H.W. Leong, and W. Luk, “A synthesizable datapath-oriented embedded FPGA fabric for silicon debug applications,” ACM Trans. Reconfigurable Technlogy and Systems (TRETS), vol.1, no.1, archicle no.7, March 2008.

3. [3] mentra Inc., eFPGA Overview, http://www.menta.fr/

4. [4] F.L. Kastensmidt, L. Carro, and R. Reis, Fault-Tolerance Techniques for SRAM-Based FPGAs (Frontiers in Electronic Testing), Springer-Verlag New York, p.180, 2006.

5. [5] L. Sterpone, Electronics System Design Techniques for Safety Critical Applications, Springer Netherlands, Netherlands, 2008.

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