Modeling of interelectrode parasitic elements of V-groove SiC MOSFET
Author:
Affiliation:
1. Department of Communications and Computer Engineering, Graduate School of Informatics, Kyoto University
2. Graduate School of Information Science, Nara Institute of Science and Technology
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Rehabilitation,Physical Therapy, Sports Therapy and Rehabilitation,General Medicine
Link
https://www.jstage.jst.go.jp/article/nolta/9/3/9_344/_pdf
Reference22 articles.
1. [1] B.J. Baliga, Fundamentals of Power Semiconductor Devices, Springer Science & Business Media, 2008.
2. [2] T. Kimoto and J.A. Cooper, Fundamentals of Silicon Carbide Technology: Growth, Characterization, Devices and Applications, Wiley-IEEE Press, 2014.
3. [3] T. Nakamura, Y. Nakano, M. Aketa, R. Nakamura, S. Mitani, H. Sakairi, and Y. Yokotsuji, “High performance SiC trench devices with ultra-low ron,” in IEEE International Electron Devices Meeting Technical Digest, pp. 26.5.1-26.5.3, 2011.
4. [4] T. Hiyoshi, K. Uchida, M. Sakai, M. Furumai, T. Tsuno, and Y. Mikamura, “Gate oxide reliability of 4H-SiCV-groove trench MOSFET under various stress conditions,” in Proceedings of International Symposium Power Semiconductor Devices and ICs, pp. 39-42, 2016.
5. [5] Y. Nakamura, M. Shintani, K. Oishi, T. Sato, and T. Hikihara, “A simulation model for SiC power MOSFET based on surface potential,” in Proceedings of International Conference on Simulation of Semiconductor Processes and Devices, pp. 121-124, September 2016.
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