Application dependent FPGA interconnect test method with small test configuration number using SMT net-grouping constraints
Author:
Affiliation:
1. Dept. of Microelectronics, Fudan University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Link
https://www.jstage.jst.go.jp/article/elex/advpub/0/advpub_21.20230495/_pdf
Reference32 articles.
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2. [2] T. Nirmalraj, et al.: “Automatic diagnosis of single fault in interconnect testing of SRAM-based FPGA”. IET Computers & Digital Techniques (2021).
3. [3] S. Banik, et al: “Application-Dependent Testing of FPGA Interconnect Network,” IEEE Trans. on Very Large Scale Integration Systems (2019) DOI: 10.1109/TVLSI.2019.2925932).
4. [4] Renovell, M.: “Some Aspects of the Test Generation Problem for an Application-Oriented Test of SRAM-Based FPGAs,” Journal of Circuits, Systems and Computers 12 (2003) 143 (DOI: 10.1142/s0218126603000714).
5. [5] Z. Yang, et al.: “A new automatic method for testing interconnect resources in FPGAs based on general routing matrix,” IEICE Electronics Express 12 (2015) 20150747-20150747.
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