An integrated capacitor-less LDO with transient and stability enhancement
Author:
Affiliation:
1. Institute of Microelectronics of the Chinese Academy of Sciences
2. University of Chinese Academy of Sciences
3. Key Laboratory of Science and Technology on Silicon Devices, Chinese Academy of Sciences
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Link
https://www.jstage.jst.go.jp/article/elex/21/9/21_21.20240199/_pdf
Reference30 articles.
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2. [2] A. Maity and A. Patra: “A single-stage low-dropout regulator with a wide dynamic range for generic applications,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 24 (2016) 2117 (DOI: 10.1109/TVLSI.2015.2503048).
3. [3] M.A. Sobhan Bhuiyan, et al.: “CMOS low-dropout voltage regulator design trends: an overview,” Electronics 11 (2022) 193 (DOI: 10.3390/electronics11020193).
4. [4] M.M. Boanloo and M. Yavari: “A low-power high-gain low-dropout regulator for implantable biomedical applications,” Circuits Syst. Signal Process. 40 (2021) 1041 (DOI: 10.1007/s00034-020-01520-9).
5. [5] J.S. Kim, et al.: “Design of a low-power and area-efficient LDO regulator using a negative-R-assisted technique,” IEEE Trans. Circuits Syst. II, Exp. Briefs 70 (2023) 3892 (DOI: 10.1109/TCSII.2023.3289497).
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