Affiliation:
1. Department of Electronics & Electrical Engineering, University of Dankook
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Reference5 articles.
1. [1] J. B. Huang, et al., “ESD protection design for advanced CMOS,” Proc. SPIE, pp.123-131, 2001.
2. [2] M.-D. Ker and C.-C. Yen, “Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test,” IEEE J. Solid-State Circuits, vol. 43, no. 11, 2008.
3. [3] K. Bock, et al., “Influence of Gate Length on ESD Performance for Deep Submicron CMOS Technology,” Proc. EOS/ESD Symp., pp. 95-104, 1999.
4. [4] V. Vashchenko, A. Concannon, M. ter Beek, and P. Hopper, High holding voltage cascaded LVTSCR structures for 5.5-V tolerant ESD protection clamps, IEEE Trans. Device Mater. Rel., vol. 4, pp. 273-280, 2004.
5. [5] E. Ground and M. Hernandez, “Obtaining TLP-like information from an HBM simulator,” EOS/ESD Symp., pp 2A.3-1-2A.3-7, 2007.
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