ESD protection design for advanced CMOS
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SPIE
Cited by 21 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A New Low Trigger SCR with Latch up Immunity for 5V Application;2018 2nd European Conference on Electrical Engineering and Computer Science (EECS);2018-12
2. SCR-Based ESD Protection Using a Penta-Well for 5 V Applications;IEEE Journal of the Electron Devices Society;2018
3. A Low-Leakage, Robust ESD Clamp with Thyristor Delay Element in 65 nm CMOS Technology;2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI);2016-07
4. A Design of BJT-based ESD Protection Device combining SCR for High Voltage Power Clamps;JSTS:Journal of Semiconductor Technology and Science;2014-06-30
5. Characterization of Nanowire Devices Under Electrostatic Discharge Stress Conditions;Nanowire Field Effect Transistors: Principles and Applications;2013-10-23
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