Low-delay parallel Chien search architecture for RS decoder
Author:
Affiliation:
1. College of Electronic and Information Engineering, Nanjing University of Aeronautics and Astronautics
2. College of Electrical Engineering, Anhui Polytechnic University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/elex/13/19/13_13.20160729/_pdf
Reference12 articles.
1. [1] Y. Chen and K. K. Parhi: “Small area parallel Chien search architectures for long BCH codes,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 12 (2004) 545 (DOI: 10.1109/TVLSI.2004.826203).
2. [2] Q. Hu, et al.: “Low complexity parallel Chien search architecture for RS decoder,” Proc. IEEE Int. Symp. Circuits & Syst. 1 (2005) 340.
3. [3] J. Cho and W. Sung: “Strength-reduced parallel Chien search architecture for strong BCH codes,” IEEE Trans. Circuits Syst. II, Exp. Briefs 55 (2008) 427 (DOI: 10.1109/TCSII.2007.914898).
4. [4] Y. Leeet al.: “Low-complexity parallel Chien search structure using two-dimensional optimization,” IEEE Trans. Circuits Syst. II, Exp. Briefs 58 (2011) 522 (DOI: 10.1109/TCSII.2011.2158709).
5. [5] X. Liet al.: “Efficient architecture for algebraic soft-decision decoding of Reed-Solomon codes,” IET Commun. 9 (2015) 10 (DOI: 10.1049/iet-com.2014.0460).
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