A full matrix joint optimization method for hardware implementation of AES MixColumns/InvMixColumns-Reference-Cited by-同舟云学术

A full matrix joint optimization method for hardware implementation of AES MixColumns/InvMixColumns

Published:2020-12-25 Issue:24 Volume:17 Page:20200391-20200391
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

ZHANG Xiaoqiang¹²³,YANG Fan¹²,ZHENG Xinxing⁴,ZHANG Xinggan³,WU Ning⁵

Affiliation:

1. Key Laboratory of Advanced Perception and Intelligent Control of High-end Equipment, Ministry of Education

2. College of Electrical Engineering, Anhui Polytechnic University

3. School of Electronic Science and Engineering, Nanjing University

4. College of Information Engineering, Wuhu Institute of Technology

5. College of Electronic and Information Engineering, Nanjing University of Aeronautics and Astronautics

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/17/24/17_17.20200391/_pdf

Reference31 articles.

1. [1] National Institute of Standards and Technology (NIST): Advanced Encryption Standard (AES) FIPS Publication 197 (2001) http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf.

2. [2] M.M. Wong, et al.: “Composite field GF(((2²)²)²) Advanced Encryption Standard (AES) S-box with algebraic normal form representation in the subfield inversion,” IET Circuits Dev. Syst. 5 (2011) 471 (DOI: 10.1049/iet-cds.2010.0435).

3. [3] M.M. Wong, et al.: “Construction of optimum composite field architecture for compact high-throughput AES S-boxes,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 20 (2012) 1151 (DOI: 10.1109/TVLSI.2011.2141693).

4. [4] X. Zhang and K.K. Parhi: “Implementation approaches for the advanced encryption standard algorithm,” IEEE Circuits and Systems Magazine 2 (2002) 24 (DOI: 10.1109/MCAS.2002.1173133).

5. [5] Y.-K. Lai, et al.: “A novel memoryless AES cipher architecture for networking applications,” Proc. IEEE Int. Symposium on Circuits and Systems (ISCAS’04) (2004) IV-333 (DOI: 10.1109/ISCAS.2004.1329008).