A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation
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Published:2014
Issue:4
Volume:E97.C
Page:332-341
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ISSN:0916-8524
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Container-title:IEICE Transactions on Electronics
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language:en
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Short-container-title:IEICE Trans. Electron.
Author:
NAKATA Yohei1, KIMI Yuta1, OKUMURA Shunsuke1, JUNG Jinwook1, SAWADA Takuya1, TOSHIKAWA Taku1, NAGATA Makoto12, NAKANO Hirofumi3, YABUUCHI Makoto3, FUJIWARA Hidehiro3, NII Koji3, KAWAI Hiroyuki3, KAWAGUCHI Hiroshi1, YOSHIMOTO Masahiko12
Affiliation:
1. Kobe University 2. JST CREST 3. Renesas Electronics Corporation
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Reference14 articles.
1. [1] K.A. Bowman, C. Tokunaga, J.W. Tschanz, A. Raychowdhury, M.M. Khellah, B.M. Geuskens, S.L. Lu, S. Member, P.A. Aseron, T. Karnik, and V. De, “All-digital circuit-level dynamic variation monitor for silicon debug and adaptive clock control,” IEEE Trans. Circuits Syst. I, vol.58, no.9, pp.2017-2025, Sept. 2011. 2. [2] K.A. Bowman, J.W. Tschanz, S.L. Lu, S. Member, P.A. Aseron, M.M. Khellah, A. Raychowdhury, B.M. Geuskens, C. Tokunaga, C.B. Wilkerson, T. Karnik, and V. De, “A 45nm resilient microprocessor core for dynamic variation tolerance,” IEEE J. Solid-State Circuits, vol.46, no.1, pp.194-208, Jan. 2011. 3. [3] J. Tschanz, N.S. Kim, S. Dighe, J. Howard, G. Ruhl, S. Vangal, S. Narendra, Y. Hoskote, H. Wilson, C. Lam, M. Shuman, C. Tokunaga, D. Somasekhar, S. Tang, D. Finan, T. Karnik, N. Borkar, N. Kurd, and V. De, “Adaptive frequency and biasing techniques for tolerance to dynamic temperature-voltage variations and aging,” ISSCC Dig. of Tech. Papers, pp.292-293, Feb. 2007. 4. [4] A. Raychowdhury, B. Geuskens, K. Bowman, J. Tschanz, S.L. Lu, T. Karnik, M. Khellah, and V. De, “Tunable replica bits for dynamic variation tolerance in 8T SRAM arrays,” IEEE J. Solid-State Circuits, vol.46, no.4, pp.797-805, April 2011. 5. [5] J. Lee, Y.J. Lee, and Y.B. Kim, “SRAM Word-oriented redundancy methodology using built in self-repair,” Proc. IEEE Intl. System-on-Chip Conference (SOCC), pp.219-222, Sept. 2004.
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