In-Situ N2-Plasma Nitridation for High-k HfN Gate Insulator Formed by Electron Cyclotron Resonance Plasma Sputtering

Author:

OHMI Shun-ichiro1,ISHIMATSU Shin1,HORIUCHI Yuske1,KUDOH Sohya1

Affiliation:

1. Tokyo Institute of Technology

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Reference18 articles.

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2. [2] J. Suh, A.C. Meng, M. Jaikisson, M. Braun, T.R. Kim, A.F. Marshall, A. Pakzad, P.C. McIntyre, and K.C. Saraswat, “3D-stacked Strained SiGe/Ge Gate-All-Arouund (GAA) Structure Fabricated by 3D Ge Condensation,” 77th Device Research Conference, Conf. Dig., 233, 2019.

3. [3] F. Khan, M.S. Han, D. Moy, R. Katz, L. Jiang, E. Banghart, N. Robson, T. Kihihata, J.C.S. Woo, and S.S. Iyer, “Design Optimization and Modeling of Charge Trap Transistors (CTTs) in 14 nm FinFET Technologies,” IEEE Electron Device Lett., vol.40, no.7, pp.1100-1103, 2019. 10.1109/led.2019.2919871

4. [4] Z.-H. Li, Y.-L. Jiang, R.-L. Li, Y.-W. Zhang, and Y.-F. Cao, “Performance Improvement by Cold Xe Pre-Amorphization Implant for Nickel Silicidation of 28-nm PMOSFET,” IEEE Electron Device Lett., vol.40, no.5, pp.777-779, 2019. 10.1109/led.2019.2907688

5. [5] P. Kushwaha, H. Agarwal, Y.-K. Lin, A. Dasgupta, M.-Y. Kao, Y. Lu, Y. Yue, X. Chen, J. Wang, W. Sy, F. Yang, P.C. Chidambaram, S. Salahuddin, and C. Hu, “Characterization and Modeling of Flicker Noise in FinFETs at Advanced Technology Node,” IEEE Electron Device Lett., vol.40, no.6, pp.985-988, 2019. 10.1109/led.2019.2911614

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