A Harmonic-Free All Digital Delay-Locked Loop Using an Improved Fast-Locking Successive Approximation Register-Controlled Scheme-Reference-Cited by-同舟云学术

A Harmonic-Free All Digital Delay-Locked Loop Using an Improved Fast-Locking Successive Approximation Register-Controlled Scheme

Published:2009 Issue:12 Volume:E92-C Page:1541-1544
ISSN:0916-8524
Container-title:IEICE Transactions on Electronics
language:en
Short-container-title:IEICE Trans. Electron.

Author:

HUANG Kai¹,CAI Zhikuang¹,CHEN Xin¹,SHI Longxing¹

Affiliation:

1. National ASIC System Engineering Research Center, Southeast University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://www.jstage.jst.go.jp/article/transele/E92.C/12/E92.C_12_1541/_pdf

Reference7 articles.

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2. [2] Y. Okajima, M. Taguchi, M. Yanagawa, K. Nishimura, and O. Hamada, “Digital delay locked loop and design technique for high-speed synchronous interface, ” IEICE Trans. Electron., vol.E79-C, no.6, pp.798-807, June 1996.

3. [3] R.-J. Yang and S.-I. Liu, “A wide-range multiphase delay-locked loop using mixed-mode VCDLs, ” IEICE Trans. Electron., vol.E88-C, no.6, pp.1248-1252, June 2005.

4. Nonredundant successive approximation register for A/D converters

5. A 40–550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm

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