Affiliation:
1. Faculty of Engineering, Shizuoka University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Reference16 articles.
1. [1] F. Masuoka, M. Momodomi, Y. Iwata, and R. Shirota, “New ultra high density EPROM and Flash EEPROM with NAND structure cell,” in IEDM Tech. Dig., pp.552-555, 1987. 10.1109/iedm.1987.191485
2. [2] M. Sako, Y. Watanabe, T. Nakajima, J. Sato, K. Muraoka, M. Fujiu, F. Kouno, M. Nakagawa, M. Masuda, K. Kato, Y. Terada, Y. Shimizu, M. Honma, A. Imamoto, T. Araya, H. Konno, T. Okanaga, T. Fujimura, X. Wang, M. Muramoto, M. Kamoshida, M. Kohno, Y. Suzuki, T. Hashiguchi, T. Kobayashi, M. Yamaoka, and R. Yamashita, “7.1 A low-power 64Gb MLC NAND-flash memory in 15nm CMOS technology,” in IEEE Int. Solid-State Circuit Conf. Dig. Tech. Papers, pp.128-130, Feb. 2015. 10.1109/isscc.2015.7062959
3. [3] T. Endoh, K. Kinoshita, T. Tanigami et al., “Novel ultrahigh-density Flash memory with a stacked surrounding gate transistor (S-SGT) structured cell,” in IEDM Tech. Dig., pp.33-36, 2001.
4. [4] E.-K. Lai, H.-T. Lue, Y.-H. Hsiao, J.-Y. Hsieh, C.-P. Lu, S.-Y. Wang, L.-W. Yang, T. Yang, K.-C. Chen, J. Gong, K.-Y. Hsieh, R. Liu, and C.-Y. Lu, “A multi-layer stackable thin-film transistor (TFT) NAND-type Flash memory,” in IEDM Tech. Dig., pp.1-4, 2006. 10.1109/iedm.2006.346903
5. [5] H. Tanaka, M. Kido, K. Yahashi, M. Oomura, R. Katsumata, M. Kito, Y. Fukuzumi, M. Sato, Y. Nagata, Y. Matsuoka, Y. Iwata, H. Aochi, and A. Nitayama, “Bit cost scalable technology with punch and plug process for ultra-high density Flash memory,” in Proc. IEEE Symp. VLSI Tech., pp.14-15, June 2007. 10.1109/vlsit.2007.4339708
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