PdEr-Silicide Formation and Contact Resistivity Reduction to n-Si(100) Realized by Dopant Segregation Process
Author:
Affiliation:
1. Tokyo Institute of Technology
2. TANAKA Kikinzoku Kogyo Co., Ltd.
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/transele/E101.C/5/E101.C_311/_pdf
Reference26 articles.
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3. [3] S. Ohmi, “Importance of Si surface flatness to realize high-performance Si devices utilizing ultrathin films with new material system,” IEICE Electron. Express, vol.11, no.14, p.20142006, 2014. 10.1587/elex.11.20142006
4. [4] H.-S. Wong, L. Chan, G. Samudra, and Y.-C. Yeo, “Sub-0.1-eV Effective Schottky-Barrier Height for NiSi on n-Type Si (100) Using Antimony Segregation,” IEEE Electron Device Lett., vol.28, no.8, pp.703-705, 2007. 10.1109/led.2007.901668
5. [5] M. Mizuno, T. Yamaguchi, X. Pages, K. Vanormelingen, M. Smits, E. Granneman, M. Fujisawa, and N. Hattori, “NiPt silicide agglomeration accompanied by stress relaxation in NiSi(010) || Si(001) grains,” Jpn. J. Appl. Phys., vol.54, no.4S, 04DA09, 2015. 10.7567/jjap.54.04da09
Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. The Evaluation of the Interface Properties of PdEr-Silicide on Si(100) Formed with TiN Encapsulating Layer and Dopant Segregation Process;IEICE Transactions on Electronics;2020-06-01
2. Etching Control of HfN Encapsulating Layer for PtHf-Silicide Formation with Dopant Segregation Process;IEICE Transactions on Electronics;2019-06-01
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