A Novel and Very Fast 4-2 Compressor for High Speed Arithmetic Operations-Reference-Cited by-同舟云学术

A Novel and Very Fast 4-2 Compressor for High Speed Arithmetic Operations

Published:2012 Issue:4 Volume:E95.C Page:710-712
ISSN:0916-8524
Container-title:IEICE Transactions on Electronics
language:en
Short-container-title:IEICE Trans. Electron.

Author:

FATHI Amir¹,AZIZIAN Sarkis¹,HADIDI Khayrollah¹,KHOEI Abdollah¹

Affiliation:

1. Microelectronic Research Laboratory of Urmia University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/transele/E95.C/4/E95.C_4_710/_pdf

Reference5 articles.

1. [1] C.-H. Chang, J. Gu, and M. Zhang, “Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits,” TCAS-I, vol.51, no.10, pp.1985-1997, 2004.

2. A 4.4 ns CMOS 54×54-b multiplier using pass-transistor multiplexer

3. [3] J. Mori, M. Nagamatsu, M. Hirano, et al., “A 10ns 544-bit parallel structured full array multiplier with 0.5µm CMOS technology,” 1990 Symposium on VLSI Circuits, Digest of Technical Papers, pp.125-126, June 1990.

4. [4] D. Shim and W. Kim, “The design of 16×16 wave pipelined multiplier using fan-in equalization technique,” Proc. 40th MWSCAS, vol.1, pp.336-339, 1997.

5. [5] D. Radhakrishnan and A.P. Preethy, “Low Power CMOS Pass Logic 4-2 Compressor for High-Speed Multiplication,” Proc. 43rd MWSCAS, vol.3, pp.1296-1298, 2000.

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