Analysis of De-Embedding Error Cancellation in Cascade Circuit Design-Reference-Cited by-同舟云学术

Analysis of De-Embedding Error Cancellation in Cascade Circuit Design

Published:2011 Issue:10 Volume:E94-C Page:1641-1649
ISSN:0916-8524
Container-title:IEICE Transactions on Electronics
language:en
Short-container-title:IEICE Trans. Electron.

Author:

TAKANO Kyoya¹²,FUJIMOTO Ryuichi³,KATAYAMA Kosuke¹,MOTOYOSHI Mizuki¹²,FUJISHIMA Minoru¹

Affiliation:

1. Graduate School of Advanced Sciences of Matter, Hiroshima University

2. Graduate School of Engineering, The University of Tokyo

3. Semiconductor & Storage Company, Toshiba Corp.

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://www.jstage.jst.go.jp/article/transele/E94.C/10/E94.C_10_1641/_pdf

Reference14 articles.

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2. A three-step method for the de-embedding of high-frequency S-parameter measurements

3. [3] Y. Tretiakov, K. Vaed, D. Ahlgren, J. Rascoe, S. Venkatadri, and W. Woods, “On-wafer de-embedding techniques for SiGe/BiCMOS/RFCMOS transmission line interconnect characterization,” Proc. Int. Intercon. Tech. Conf., pp.166-168, June 2004.

4. [4] Y. Goto, Y. Natsukari, and M. Fujishima, “New on-chip de-embedding for accurate evaluation of symmetric devices,” Jpn. J. Appl. Phys., vol.47, no.4, pp.2812-2816, 2008.

5. [5] E.S. Daniel, N.E. Harff, V. Sokolov, S.M. Schreiber, and B.K. Gilbert, “Network analyzer measurement de-embedding utilizing a distributed transmission matrix bisection of a single THRU structure,” 63rd ARFTG Conf., pp.61-68, June 2004.

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