Design and Investigation of Silicon Gate-All-Around Junctionless Field-Effect Transistor Using a Step Thickness Gate Oxide
Author:
Affiliation:
1. University of London (LSE)
2. Micron Technology, Inc.
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/transele/E104.C/8/E104.C_2020ECP5042/_pdf
Reference31 articles.
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2. [2] S. Furukawa, H. Matsumura, and H. Ishiwara, “Theoretical Considerations on Lateral Spread of Implanted Ions,” Jpn. J. Appl. Phys., vol.11, no.2, pp.134-142, 1972. 10.1143/jjap.11.134
3. [3] A. Chaudhry and M.J. Kumar, “Controlling Short-Channel Effects in Deep-Submicron SOI MOSFETs for Improved Reliability,” IEEE Trans. Device Mater. Reliab., vol.4, no.1, pp.99-109, 2004. 10.1109/tdmr.2004.824359
4. [4] International Roadmap for Devices and Systems (IRDS) 2018 Ed., IEEE, 2018.
5. [5] K.J. Kuhu, “Considerations for Ultimate CMOS Scaling,” IEEE Trans. Electron Devices, vol.59, no.7, pp.1813-1828, 2012. 10.1109/ted.2012.2193129
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