On Reducing Test Power, Volume and Routing Cost by Chain Reordering and Test Compression Techniques-Reference-Cited by-同舟云学术

On Reducing Test Power, Volume and Routing Cost by Chain Reordering and Test Compression Techniques

Published:2010 Issue:3 Volume:E93-C Page:369-378
ISSN:0916-8524
Container-title:IEICE Transactions on Electronics
language:en
Short-container-title:IEICE Trans. Electron.

Author:

LIN Chia-Yi¹,HSU Li-Chung²,CHEN Hung-Ming¹

Affiliation:

1. Department of Electronics Engineering, National Chiao Tung University

2. Springsoft Co.

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://www.jstage.jst.go.jp/article/transele/E93.C/3/E93.C_3_369/_pdf

Reference39 articles.

1. [1] A. Crouch, Design-for-Test for Digital IC's and Embedded Core Systems, Prentice Hall, 1999.

2. [2] N. Nicolici and B.M. Al-Hashimi, Power-Constrained Testing of VLSI Circuits, Kluwer Academic Publishers, 2003.

3. [3] S. Kajihara, K. Taniguchi, K. Miyase, I. Pomeranz, and S.M. Reddy, “Test data compression using don't-care identification and statistical encoding,” Proc. Asian Test Symposium, pp.67-72, 2002.

4. [4] M. Nourani and M.H. Tehranipour, “RL-Huffman encoding for test compression and power reduction in scan applications,” ACM Trans. Des. Autom. Electron. Syst., vol.10, no.1, pp.91-115, Jan. 2005.

5. [5] I. Lee, Y.M. Hur, and T. Ambler, “The efficient multiple scan chain architecture reducing power dissipation and test time,” Proc. IEEE Asian Test Symposium, pp.94-97, 2004.

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