Design Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using gm/ID Lookup Table Methodology-Reference-Cited by-同舟云学术

Design Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using gm/ID Lookup Table Methodology

Published:2011 Issue:3 Volume:E94-C Page:334-345
ISSN:0916-8524
Container-title:IEICE Transactions on Electronics
language:en
Short-container-title:IEICE Trans. Electron.

Author:

KONISHI Takayuki¹,INAZU Kenji¹,LEE Jun Gyu¹,NATSUI Masanori¹,MASUI Shoichi¹,MURMANN Boris²

Affiliation:

1. Tohoku University

2. Stanford University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://www.jstage.jst.go.jp/article/transele/E94.C/3/E94.C_3_334/_pdf

Reference18 articles.

1. [1] D. Buss, “Technology in the Internet age,” IEEE ISSCC Dig. Tech. papers, pp.18-21, 2002.

2. [2] Virtuoso Neocircuit, datasheet, http://cadence.com/rl/Resources/datasheets/VirNeoCircuit_ds.pdf accessed April 4, 2010.

3. A g/sub m//I/sub D/ based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA

4. [4] P. Jespers, A g_m/I_D Methodology: A Sizing Tool for Low-Voltage Analog CMOS Circuits, Springer, New York, 2009.

5. [5] B. Murmann, “Design and optimization of operational transconductance amplifiers in fine-line CMOS,” IEEE Custom Integrated Circuit Conference (CICC) Educational Session, 2008.

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