Layout-Aware Variability Characterization of CMOS Current Sources-Reference-Cited by-同舟云学术

Layout-Aware Variability Characterization of CMOS Current Sources

Published:2012 Issue:4 Volume:E95.C Page:696-705
ISSN:0916-8524
Container-title:IEICE Transactions on Electronics
language:en
Short-container-title:IEICE Trans. Electron.

Author:

LIU Bo¹,YANG Bo¹,NAKATAKE Shigetoshi¹

Affiliation:

1. University of Kitakyushu

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/transele/E95.C/4/E95.C_4_696/_pdf

Reference20 articles.

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2. [2] M. Yamamoto, H. Endo, and H. Masuda, “Development of a large-scale TEG for evaluation and analysis of yield and variation,” Proc. ICMTS, pp.53-58, 2003.

3. Analysis and Characterization of Device Variations in an LSI Chip Using an Integrated Device Matrix Array

4. [4] X. Qi, A. Gyure, Y. Luo, S.C. Lo, M. Shahram, and K. Singhal, “Measurement and characterization of pattern dependent process variations of interconnect resistance, capacitance and inductance in nanometer technologies,” Proc. 16th ACM Great Lakes symposium on VLSI, pp.14-18, 2006.

5. [5] P.M. O'Neill, P. George, and H. Aoki, “A complete CMOS SPICE model generation system,” 1995 HP Design Technology Conf. Proc., pp.79-86, 1995.

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