A novel architecture for low voltage-low power DLL-based frequency multipliers-Reference-Cited by-同舟云学术

A novel architecture for low voltage-low power DLL-based frequency multipliers

Published:2011 Issue:11 Volume:8 Page:859-865
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Gholami M.¹,Ardeshir Gh.¹,Ghonoodi H.¹

Affiliation:

1. Department of Electrical Engineering, Babol University of Technology

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

http://www.jstage.jst.go.jp/article/elex/8/11/8_11_859/_pdf

Reference7 articles.

1. [1] H. J. Hsu, C. T. Chiu, and Y. S. Hsu, “Design of ultra low power current mode logics with adaptive body bias,” IEEE ISSOC, pp. 141-144, Sept. 2000.

2. A 900-MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications

3. [3] B. Razavi, Design of Analog CMOS Integrated Circits, McGraw-Hill.

4. [4] S. Sidiropoulos, D. Liu, J. Kim, G. Wei, and M. Horowitz, “Adaptive bandwidth DLLs and PLLs using regulated supply CMOS buffers,” Proc. IEEE Symp. VLSI Circuits, pp. 124-127, June 2000.

5. A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips

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