A 16-bit 8-MS/s SAR ADC with a foreground calibration and hybrid-charge-supply power structure

Author:

Zhang Zhenwei12,Qiu Lei3,Shan Yi1,Dong Yemin14

Affiliation:

1. State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences

2. University of Chinese Academy of Sciences

3. Tongji University

4. Center of Materials Science and Optoelectronics Engineering, University of Chinese Academy of Sciences

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference30 articles.

1. [1] Y.-H. Chung, et al.: “A 102dB-SFDR 16-bit calibration-free SAR ADC in 180-nm CMOS,” IEEE APCCAS (2019) 5 (DOI: 10.1109/APCCAS47518.2019.8953163).

2. [2] C. Rhee, et al.: “8.4-to-16-bit resolution, 1-to-16 kHz bandwidth ADC with programmable-gain functionality for multi-sensor applications,” Electron. Lett. 55 (2019) 982 (DOI: 10.1049/el.2019.1496).

3. [3] S. Li, et al.: “A 13-ENOB second-order noise-shaping SAR ADC realizing optimized NTF zeros using the error-feedback structure,” IEEE J. Solid-State Circuits 53 (2018) 3484 (DOI: 10.1109/JSSC.2018.2871081).

4. [4] A. Bannon, et al.: “An 18 b 5 MS/s SAR ADC with 100.2 dB dynamic range,” IEEE Symp. VLSI Circuits Dig. Tech. Papers (2014) 33 (DOI: 10.1109/VLSIC.2014.6858371).

5. [5] D. Hummerston, et al.: “An 18-bit 2MS/s pipelined SAR ADC utilizing a sampling distortion cancellation circuit with -107 dB THD at 100 kHz,” IEEE Symp. VLSI Circuits Dig. Tech. Papers (2017) 280 (DOI: 10.23919/VLSIC.2017.8008508).

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