A wideband low-jitter PLL with an optimized Ring-VCO-Reference-Cited by-同舟云学术

A wideband low-jitter PLL with an optimized Ring-VCO

Published:2020 Issue:3 Volume:17 Page:20190703-20190703
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Zou Wei¹,Ren Daming¹,Zou Xuecheng¹

Affiliation:

1. School of Optical and Electronic Information, Huazhong University of Science and Technology

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/17/3/17_17.20190703/_pdf

Reference31 articles.

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3. [3] G. Shu, et al.: “A 4-to-10.5 Gb/s continuous-rate digital clock and data recovery with automatic frequency acquisition,” IEEE J. Solid-State Circuits 51 (2016) 428 (DOI: 10.1109/JSSC.2015.2497963).

4. [4] R. B. Staszewski, et al.: “All-digital PLL and transmitter for mobile phones,” IEEE J. Solid-State Circuits 40 (2005) 2469 (DOI: 10.1109/JSSC.2005.857417).

5. [5] Y. W. Li, et al.: “A reconfigurable distributed all-digital clock generator core with SSC and skew correction in 22 nm high-k tri-gate LP CMOS,” ISSCC Dig. Tech. Papers (2012) 70 (DOI: 10.1109/ISSCC.2012.6176934).

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