TLC STT-MRAM aware LLC for multicore processor

Author:

Park Taejin1,Hur Jae Young2,Jang Wooyoung1

Affiliation:

1. Department of Electronics and Electrical Engineering, Dankook University

2. Faculty of Engineering, Vietnamese-German University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference31 articles.

1. [1] Y. Kwon and M. Rhu: “A Disaggregated memory system for deep learning,” IEEE Micro 39 (2019) 82 (DOI: 10.1109/MM.2019.2929165).

2. [2] D. Chatzopoulos, et al.: “Mobile augmented reality survey: from where we are to where we go,” IEEE Access 5 (2017) 6917 (DOI: 10.1109/ACCESS.2017.2698164).

3. [3] G. Pastuszak and A. Abramowski: “Algorithm and architecture design of the H.265/HEVC intra encoder,” IEEE Trans. Circuits Syst. Video Technol. 26 (2016) 210 (DOI: 10.1109/TCSVT.2015.2428571).

4. [4] W. Jang: “Screen orientation aware DRAM architecture for mobile video and graphic applications,” IEEE Trans. Circuits Syst. Video Technol. 28 (2018) 3527 (DOI: 10.1109/TCSVT.2017.2715062).

5. [5] B.M. Rogers, et al.: “Scaling the bandwidth wall: challenges in and avenues for CMP scaling,” ACM SIGARCH Computer Architecture News 37 (2009) 371 (DOI: 10.1145/1555815.1555801).

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