A low-jitter 2.4 GHz all-digital MDLL with a dithering jitter reduction scheme for 256 times frequency multiplication

Author:

Park Dongjun12,Kim Jongsun1

Affiliation:

1. Electronic and Electrical Engineering, Hongik University

2. Samsung Electronics, System LSI

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference30 articles.

1. [1] N.D. Dalt, et al.: “A compact triple-band low-jitter digital LC PLL with programmable coil in 130-nm CMOS,” IEEE J. Solid-State Circuits 40 (2005) 1482 (DOI: 10.1109/JSSC.2005.847325).

2. [2] N.D. Dalt: “A design-oriented study of the nonlinear dynamics of digital bang-bang PLLs,” IEEE Trans. Circuits Syst. I, Reg. Papers 52 (2005) 21 (DOI: 10.1109/TCSI.2004.840089).

3. [3] R.B. Staszewski, et al.: “All-digital PLL and transmitter for mobile phones,” IEEE J. Solid-State Circuits 40 (2005) 2469 (DOI: 10.1109/JSSC.2005.857417).

4. [4] J. Lin, et al.: “A PVT tolerant 0.18 MHz to 600 MHz self-calibrated digital PLL in 90 nm CMOS process,” IEEE ISSCC Dig. Tech. Papers (2004) 488 (DOI: 10.1109/ISSCC.2004.1332807).

5. [5] S.-Y. Yang, et al.: “A 7.1 mW, 10 GHz all-digital frequency synthesizer with dynamically reconfigured digital loop filter in 90 nm CMOS technology,” IEEE J. Solid-State Circuits 45 (2010) 578 (DOI: 10.1109/JSSC.2009.2039530).

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