Power switch implementation for low voltage digital circuits

Author:

Kim Kyung Ki1

Affiliation:

1. School of Electronic Engineering, Daegu University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference5 articles.

1. [1] K. Shi and D. Howard, “Challenges in sleep transistor design and implementation in low-power designs,” IEEE DAC, pp. 113-116, July 2006.

2. [2] K. Min and T. Sakurai, “Zigzag Super Cut-off CMOS (ZSCCMOS) Scheme with Self-Saturated Virtual Power Lines for Subthreshold-Leakage-Suppressed Sub-l-V-VDD LSI’s,” ESSCIRC, pp.679-682, 2002.

3. [4] S. Kim, S. Kosonocky, D. Knebel, et al., “A multi-mode power gating structure for low-voltage deep-submicron CMOS ICs,” IEEE Trans. Circuits Syst. II, vol. 54, no. 7, pp. 327-339, July 2007.

4. [5] P. Royannez, H. Mair, F. Dahan, M. Wagner, M. Streeter, et al., “90nm low leakage Soc design techniques for wireless applications,” Proc. IEEE ISSCC, pp. 138-139, Feb. 2006.

5. [6] K. Usami, N. Kawabe, and M. Koizumi, “Automated selective multi-threshold design for ultra-low standby applications,” Proc. IEEE ISLPED, pp. 202-206, Aug. 2002.

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