Classification on variation maps: a new placement strategy to alleviate process variation on FPGA-Reference-Cited by-同舟云学术

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Classification on variation maps: a new placement strategy to alleviate process variation on FPGA

Published:2014 Issue:3 Volume:11 Page:20130912-20130912
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Guan Zhenyu¹,Wong Justin S. J.¹,Chaudhuri Sumanta¹,Constantinides George¹,Cheung Peter Y. K.¹

Affiliation:

1. Department of Electrical and Electronic, Imperial College London, South Kensington Campus

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/11/3/11_10.20130912/_pdf

Reference10 articles.

1. [1] Y. Lin, L. He and M. Hutton: IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 16 (2008) 124.

2. [2] Y. Matsumoto, M. Hioki, T. Kawanami, H. Koike, T. Tsutsumi, T. Nakagawa and T. Sekigawa: ACM Trans. Reconfigurable Tech. Syst. 1 [1] (2008) 3:1.

3. [3] P. Sedcole and P. Y. K. Cheung: ACM Trans. Reconfigurable Tech. Syst. 1 [2] (2008) 1936.

4. [4] E. Stott, Z. Guan, J. M. Levine, J. S. J. Wong and P. Y. K. Cheung: IEEE Design Test (2013) 1.

5. [5] P. Sedcole and P. Y. K. Cheung: ACM/SIGDA FPGA (2007) 178.

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