Iterative Synthesis Methods Estimating Programmable-Wire Congestion in a Dynamically Reconfigurable Processor-Reference-Cited by-同舟云学术

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Iterative Synthesis Methods Estimating Programmable-Wire Congestion in a Dynamically Reconfigurable Processor

Published:2011 Issue:12 Volume:E94-A Page:2619-2627
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

TOI Takao¹²,OKAMOTO Takumi¹,AWASHIMA Toru¹,WAKABAYASHI Kazutoshi³,AMANO Hideharu²

Affiliation:

1. Renesas Electronics Corporation

2. Keio University

3. NEC Corporation

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

http://www.jstage.jst.go.jp/article/transfun/E94.A/12/E94.A_12_2619/_pdf

Reference17 articles.

1. [1] T. Toi, N. Nakamura, Y. Kato, T. Awashima, K. Wakabayashi, and L. Jing, “High-level synthesis challenges and solutions for a dynamically reconfigurable processor,” Proc. ICCAD'06, pp.702-708, Nov. 2006.

2. [2] V. Manohararajah, G.R. Chiu, D.P. Singh, and S.D. Brown, “Predicting interconnect delay for physical synthesis in a FPGA CAD flow,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.15, no.8, pp.895-903, Aug. 2007.

3. [3] W.E. Dougherty and D.E. Thomas, “Unifying behavioral synthesis and physical design,” Proc. 37th DAC, pp.756-761, June 2000.

4. [4] T. Toi, T. Okamoto, T. Awashima, K. Wakabayashi, and H. Amano, “Wire congestion aware synthesis for a dynamically reconfigurable processor,” Proc. FPT'10, pp.300-303, Dec. 2010.

5. High-level Synthesis Challenges for Mapping a Complete Program on a Dynamically Reconfigurable Processor

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