High-level Synthesis Challenges for Mapping a Complete Program on a Dynamically Reconfigurable Processor-Reference-Cited by-同舟云学术

High-level Synthesis Challenges for Mapping a Complete Program on a Dynamically Reconfigurable Processor

Published:2010 Issue: Volume:3 Page:91-104
ISSN:1882-6687
Container-title:IPSJ Transactions on System LSI Design Methodology
language:en
Short-container-title:IPSJ Transactions on System LSI Design Methodology

Author:

Toi Takao,Nakamura Noritsugu,Kato Yoshinosuke,Awashima Toru,Wakabayashi Kazutoshi

Publisher

Information Processing Society of Japan

Subject

Electrical and Electronic Engineering,Computer Science Applications

Link

http://www.jstage.jst.go.jp/article/ipsjtsldm/3/0/3_0_91/_pdf

Reference23 articles.

1. 1) Mei, B., et al.: Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study, Proc. DATE'04, Vol.2, pp.21224-21229 (Feb. 2004).

2. 2) Amano, H., et al.: MuCCRA chips: Configurable dynamically reconfigurable processors, A-SSCC 2007, pp.384-387 (Nov. 2007).

3. 3) Motomura, M.: A Dynamically Reconfigurable Processor Architecture, Microprocessor Forum (Oct. 2002).

4. 4) Bondalapati, K.: Parallelizing DSP nested loops on reconfigurable architectures using data context switching, Proc. 38th DAC, pp.273-276, (2001).

5. 5) Sato, T., Watanabe, H. and Shibata, K.: Implementation of dynamically reconfigurable processor DAPDNA-2, VLSI Design, Automation and Test, pp.323-324 (Apr. 2005).

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