Low Power Placement and Routing for the Coarse-Grained Power Gating FPGA Architecture-Reference-Cited by-同舟云学术

Low Power Placement and Routing for the Coarse-Grained Power Gating FPGA Architecture

Published:2011 Issue:12 Volume:E94-A Page:2519-2527
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

LI Ce¹,DONG Yiping¹,WATANABE Takahiro¹

Affiliation:

1. Graduate School of Information, Production and Systems, Waseda University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

http://www.jstage.jst.go.jp/article/transfun/E94.A/12/E94.A_12_2519/_pdf

Reference23 articles.

1. [1] M. Keating, D. Flynn, R. Aitken, A. Gibbons, and K. Shi, Low Power Methodology Manual: For System-on-Chip Design, Springer Publishing Company, Incorporated, 2007.

2. [2] S. Ishihara, M. Hariyama, and M. Kameyama, “A low-power fpga based on autonomous fine-grain power-gating,” Proc. 2009 Asia and South Pacific Design Automation Conference, ASP-DAC'09, pp.119-120, IEEE Press, Piscataway, NJ, USA, 2009.

3. [3] A. Gayasen, K. Lee, N. Vijaykrishnan, M. Kandemir, M.J. Irwin, and T. Tuan, “A dual-vdd low power fpga architecture,” Proc. International Conference on Field Programmable Logic and Applications, pp.145-157, 2004.

4. Field Programmability of Supply Voltages for FPGA Power Reduction

5. [5] C.Q. Tran, H. Kawaguchi, and T. Sakurai, “95% leakage-reduced fpga using zigzag power-gating, dual-vth/vdd and micro-vdd-hopping,” Asian Solid-State Circuits Conference, 2005, pp.149-152, Nov. 2005.

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