Region Oriented Routing FPGA Architecture for Dynamic Power Gating

Author:

LI Ce1,DONG Yiping1,WATANABE Takahiro1

Affiliation:

1. Graduate School of Information, Production and Systems, Waseda University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Reference27 articles.

1. [1] Altera, Stratix IV Device Handbook, Altera Corp., Feb. 2011. http://www.altera.com/literature/hb/stratix-iv/stratix4_handbook.pdf

2. [2] Xilinx, Virtex-5 User Guide, Xilinx Inc., May 2010. http://www.xilinx.com/support/documentation/user_guides/ug190.pdf

3. [3] M. Keating, D. Flynn, R. Aitken, A. Gibbons, and K. Shi, Low Power Methodology Manual: For System-on-Chip Design, Springer Publishing Company, Incorporated, 2007.

4. [4] T. Tuan, A. Rahman, S. Das, S. Trimberger, and S. Kao, “A 90-nm low-power FPGA for battery-powered applications,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol.26, no.2, pp.296-300, Feb. 2007.

5. [5] C.Q. Tran, H. Kawaguchi, and T. Sakurai, “95% leakage-reduced FPGA using zigzag power-gating, dual-VTH/VDD and micro-VDD-hopping,” Asian Solid-State Circuits Conference, 2005, pp.149-152, Nov. 2005.

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